a poster advertising some new hardware:  # Upgrade your browsing The world’s first HTML5 accelerator card is here. Our custom chips work with Chrome and with Electron apps to give you a web experience like never before.  - One PCI Express x16 card, endless power - Supports viewports up to 7680x4320 and refresh rates up to 240Hz - Parallel renderer with on-die Flexbox and CSS Grid solvers - Shielded event bubbler for smooth, noise-free mouse movements - 8 programmable Virtual DOM chips for super-fast React apps - Seguri-Dad® TPM cryptographically signs your web requests so you never have to complete a CAPTCHA again - Low-voltage SVG rasteriser  a 3D render of the card highlights features of various chips: - Predictive JSON deserialiser - 1024-bit renderer (64 div cores, 128 span cores, 8K-ready, 256MB emoji cache) - Virtual DOM+, 8-stage diff pipeline - Dual garbage collectors  benchmark charts show that it significantly outdoes Firefox and Chrome on Max Discord Scrollback (text and GIFs loaded before client drops to under 60fps) and Facebook News Feed FPS (scrolling through the NIST Standard Minion Meme Collection)
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[–] 85 points 3 weeks ago (1 child)

I know this is a joke - but there totally is hardware acceleration for some of this stuff in modern processors. There definitely is for JS, JSON and generally string stuff. It's not even x86 only, ARM got these kinds of things as well (although likely less of it)

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  • [+] 39 points 3 weeks ago (1 child)
  • [–] 34 points 3 weeks ago (-1 children)

    The 8088 CPU (the one from the original IBM PC) had special string scanning support with both instructions and registers. The SI (source index) and DI (destination index) were such registers, and a bunch of instructions related.

    However, specialized instructions take die area on the CPU. In the 1980s a movement based on the observation that most sophisticated instructions were not used much, and it would be better to concentrate on making very common operations (like add, load, store, shift, or whatever) fast. That started reduced-instruction set computing (RISC).

    RISC was so successful that x86 chips switched to the model with a RISC-like core and implementing more sophisticated fuctions in "microcode". Today Linux can load microcode, which is basically patching the firmware of the CPU itself.

    Anyway, of course the drive towards RISC ended as people realized that some advanced functionality is really useful. In the 1990s and 2000s this was focused around new limitations: it was impossible to get higher frequencies so running a single core couldn't get faster. CPUs added SIMD (single instruction, multiple data) support as well as hyperthreading.

    Now... revisiting string operations and adding CPU support would be possible. Engineers at CPU design shops look at how their chip space is used and optimize the die area for instruction sets and also registers, cache, and so on. But my guess is that it doesn't make sense or it would have happened a decade ago already.

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  • What's amazing is that actually everything in there could be doable unironically.

    But more amazing (and embarrasing) is the fact that we have reached to this point where optimization is that undervalued by most programmers. Horrible timeline to live in, when AI is messing up with hardware prices.

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