Hi everyone. I asked a question here before about my senior design project where I was planning on creating a RISC-V cpu.

I started the project and currently using iverilog, vpp and GTKWave (can also add yosys here but not for now) for development. And I plan on using Vivado for final implementation and IP's.

Is this a good way of doing things? Should I just use Vivado? I feel like my approach is easier and lets me focus on the logic.