IBM's nanostack concept seems to separate complementary n-type and p-type transistors into vertically bonded tiers instead of placing them side by side in a single transistor layer. The payoff is a major reduction in the lateral footprint of a CMOS pair, as the architecture effectively turns one NFET+PFET structure from a 2D layout into a 3D stacked layout, which is why IBM can claim roughly double transistor density versus its 2nm research node without relying on conventional planar shrink.

My exact (and basically complete) train of though:

"isn't this physically impossible? Ohh smart"

Discount cause they’re explosive.

Same. Waiting for the shitstorm caused by recently-announced efforts by accountimg firms to use AI too! I'm sure that'll go just fine.

Just what we need, vibe-designed chips for even buggier hardware, that then gets patched with even shittier vendor vibe code. I just hope I can retire before this shit hits the market.