IBM's nanostack concept seems to separate complementary n-type and p-type transistors into vertically bonded tiers instead of placing them side by side in a single transistor layer. The payoff is a major reduction in the lateral footprint of a CMOS pair, as the architecture effectively turns one NFET+PFET structure from a 2D layout into a 3D stacked layout, which is why IBM can claim roughly double transistor density versus its 2nm research node without relying on conventional planar shrink.