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Using open source tools for FPGA development (lemmy.zip)
submitted 2 weeks ago by to c/askelectronics@discuss.tchncs.de
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Hi everyone. I asked a question here before about my senior design project where I was planning on creating a RISC-V cpu.

I started the project and currently using iverilog, vpp and GTKWave (can also add yosys here but not for now) for development. And I plan on using Vivado for final implementation and IP's.

Is this a good way of doing things? Should I just use Vivado? I feel like my approach is easier and lets me focus on the logic.

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[–] 2 points 1 week ago

One question is if you will be using some Xilinx IP, in which case the simulation models likely will be encrypted. If your project doesn't, I don't see why it would be an issue using Icarus, etc.

If all you depend on from the IP is data over an AXI/AXI-stream or the like you can use open-source bus-function models (which I understand as librarues you can use that will take care of properly driving something like an AXI interface for you) in your testbench.

I'm a student myself, Im sharing what I know but this might not be how industry does it.

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