18
PWM resolution for switch mode power supplies. (lemmy.world)
submitted 3 months ago by to c/askelectronics@discuss.tchncs.de
11 comments fedilink hide all child comments
 

So, I'm tinkering with the ATtiny 3224 and its PWM capabilities. I can get 256 bits of resolution per cycle at 78.125kHz.

If I drop to 32 bits, that gets me to 625kHz, as shown in the screenshot.

I've done some searching but I may not know the right term and I'm probably looking for a rule of thumb.

What sort of resolution do you need to regulate a DC/DC switch mode? (in this case a pure resistive load that doesn't change)

I think it might be something like a factor for required percentage of change of switch ON time. Such as, you should generally be able to modify your duty cycle by increments of 5% or 0.5% or whatever for proper regulation.

Does this factor have a name?

you are viewing a single comment's thread
view the rest of the comments
[–] 1 point 3 months ago (2 children)

I tend to agree with litchralee, changing the duty cycle is usually how these things are done rather than having multiple voltages.

From a control perspective, it's much easier to turn a digital signal on for 1/4 the time than it is to generate 1/4 the voltage for the full time. But that's just for basic PWM. If you're trying to boost the voltage up from your source though, the mechanism for getting a target voltage is a bit different, and relies on "charging up" an inductor and disconnecting it to spike the voltage. I found this reference that seems to have some good diagrams of how it works: https://analogcircuitdesign.com/boost-converter/

In a boost converter, duty cycle and frequency should be tuned to the inductor so that energy isn't being wasted after the inductor reaches steady-state and starts acting like a short circuit.

  • permalink
  • fedilink
  • source
  • parent
  • hideshow 2 child comments
    •
  • [–] [S] 1 point 3 months ago (1 child)

    I explained it poorly. The chip has an ADC that can operate in window mode. I. E. when my output voltage jitters high or low out of bound, I can use logic to very quickly effectively increase or decrease my duty cycle. (Actually substitute another pwm signal that is in pnase but with a larger or smaller duty)

    5V square PWM from the ATtiny goes to a gate driver capable of several amps at 5V, that gate driver switches a pair of logic level MOSFETs, one of the MOSFETs switching the coil and the other acting as the recitfier. Topology is a synchronus inverting buckboost.

    Changing the duty cycle then raises or lowers the voltage.

    At the same time, via interrupt or event channel, the cpu starts calculating a new duty cycle and setting the timers. Interrupts may take 100 cycles. Whereas, pwm at 625kHz will have completed an additional three cycles before I can even start to modify the duty from the program.

    None of this may matter. Static dumb resistive load, I could probably just about run my MOSFETs off a 555 and not even worry about feedback or regulation.

    However, the idea is interesting to me. Quick response regulation with more precise regulation happening as the CPU catches up.

    Seems like it would give you a flatter output.

    I've found when I discover an interesting electronic or programming technique or problem, that usually means I don't know the name. It's usually something figured out decades ago and there are references and papers that explain it and consider angles that I didn't know about.

  • permalink
  • fedilink
  • source
  • parent
  • hideshow 1 child comment
    •
  • [–] 2 points 3 months ago*

    I see, yeah that seems like a decent design going through the interrupt. Since your load is static, the responsiveness of your IC interrupts shouldn't matter too much, but if you were trying to drive a high bandwidth load, then it would start becoming an issue. 625kHz or even the effective 200kHz you have control over would be plenty accurate even for something like audio (which wouldn't change faster than maybe 48kHz). You can size your output capacitor accordingly so that if you suddenly hook up a bigger load, the voltage drop is acceptable until the IC can catch up.

    Sorry, I got a little caught on other's interpretation rather than what you were actually saying.

  • permalink
  • fedilink
  • source
  • parent