Hi everyone. I asked a question here before about my senior design project where I was planning on creating a RISC-V cpu.

I started the project and currently using iverilog, vpp and GTKWave (can also add yosys here but not for now) for development. And I plan on using Vivado for final implementation and IP's.

Is this a good way of doing things? Should I just use Vivado? I feel like my approach is easier and lets me focus on the logic.

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[–] 2 points 2 weeks ago

Xilinx is the best reason to never get into FPGA work. I have dabbled on and off over the years, but every fucking time the tool chain just leaves me exhausted and willing to sacrifice as much SWAP as necessary to get FPGAs far away from my project.

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