The node sizes are backwards computed from the unit area of a one bit SRAM cell. It used to be the physical size of the smallest structure, e.g. a transistor gate.

I agree it's highly misleading. Also, people forget that the original Moore's law publication mention constant doubling time of transistors per area per unit of cost. So people keep pointing at multichip, thinned die stacking and 5 nm WSI like Cerebras to argue Moore scaling didn't die a long time ago, but ignore costs.